Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions
US4149915A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1978 |
| Grant date | Apr 17, 1979 |
| Priority date | — |
| Expiry date | Jan 27, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/061
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating devices having overlapping heavily doped impurity regions of opposite conductivity wherein the formation of crystallographic faults emanating from the overlapping regions is eliminated. It has been discovered that crystallographic faults can be avoided by limiting the total N and P impurity concentrations in the overlapped regions. The process includes forming in the semiconductor substrate a first arsenic doped region having a maximum impurity concentration in the range of 5.times.10.sup.20 to 3.times.10.sup.21 atoms/cc, and forming in the silicon substrate a second adjacent boron doped region in partial overlapping relation to the first region having a maximum impurity concentration in the range of 5.times.10.sup.19 to 3.times.10.sup.20 atoms/cc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.