Localized oxidation enhancement for an integrated injection logic circuit
US4157268A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1977 |
| Grant date | Jun 5, 1979 |
| Priority date | — |
| Expiry date | Jun 16, 1997 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/966
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device and method are disclosed for incorporating on a single semiconductor chip, integrated injection logic (I.sup.2 L) circuits operating at low signal voltages and off chip driver devices operating at relatively high signal voltages. The vertical NPN transistor operated in an upward injection mode as is conventionally employed in I.sup.2 L circuitry, is formed with a thinner epitaxial layer between the buried subemitter and the base region than is the thicker epitaxial layer separating the buried subcollector from the base region in the downward injecting NPN vertical transistors employed as the off chip drivers and receivers on the same semiconductor chip. A method is disclosed for forming this structure which employs the technique of introducing damage in the epitaxial region above the buried subemitter of the I.sup.2 L vertical transistor so as to enhance the reactivity of the epitaxial surface to a subsequent oxidation reaction step. By increasing the rate of oxidation in the epitaxial layer, a locally thinned region can be formed, into which the base and collector structures can be subsequently formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.