Stratified charge ram having an opposite dopant polarity MOSFET switching circuit
US4158238A · kind A · utility
Inventor
Key dates
| Filing date | Apr 21, 1978 |
| Grant date | Jun 12, 1979 |
| Priority date | — |
| Expiry date | Apr 21, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A P-channel MOS stratified charge memory is formed on an N tub and controlled by peripheral N-channel MOS switches formed in the surrounding P substrate. A positive bias (+5 volts) applied to the N tub and a negative bias (-5 volts) applied to the P substrate create an isolation reverse bias therebetween. During the write mode, the row electrode of the addressed memory cell receives a positive control signal (+5 volts, zero with respect to the N tub) to establish accumulation for supporting electron conduction in the active channel under the row electrode. During the storage mode each row receives a less positive control signal (0 volts, minus five volts with respect to the N tub) to establish a depletion in the active channel thereunder which is nonconductive to both holes and electrons. During the read mode, the row of the addressed memory cell receives an even less positive control signal (-5 volts, minus ten volts with respect to the N tub) to establish inversion for supporting hole conduction in the active channel thereunder. The N dopant differential between the N+ doped row lead and the N doped active channel creates a work function slightly favorable towards electron accumu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.