Double bit error correction using double bit complementing
US4163147A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 1978 |
| Grant date | Jul 31, 1979 |
| Priority date | — |
| Expiry date | Jan 20, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improvement to a semiconductor memory subsystem containing single bit error correction/double bit error detection (SBC/DBD) which provides correction of double bit errors through the utilization of a modest amount of additional circuitry. The present invention accomplishes this result through the technique of sequentially complementing each double bit pair within the semiconductor memory subsystem data word determined to contain a multiple error and rechecking the modified data word with the existing SBC/DBD circuitry, one double bit pair at a time, until it is determined by the SBC/DBD circuitry that such double bit pair complementing has corrected the double bit error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.