Method of forming an integrated circuit structure with fully-enclosed air isolation
US4169000A · kind A · utility
55Cited by
8References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 10, 1978 |
| Grant date | Sep 25, 1979 |
| Priority date | — |
| Expiry date | May 10, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/764
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a fully-enclosed air isolation structure which comprises etching a pattern of cavities extending from one surface of a silicon substrate into the substrate to laterally surround and electrically isolate said plurality of substrate pockets, and then forming a first layer of silicon dioxide on said first substrate surface. Next, a planar second layer comprising silicon dioxide is formed over a second silicon substrate, after which this planar layer is fused to said silicon dioxide layer to thereby fully enclose said cavities. Then, the second silicon substrate is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.