Method of defining contact openings in insulating layers on semiconductor devices without the formation of undesirable pinholes
US4174252A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1978 |
| Grant date | Nov 13, 1979 |
| Priority date | — |
| Expiry date | Jul 26, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A p-n junction silicon semiconductor device passivated with a first layer of oxygen-doped polycrystalline silicon and a second layer of silicon nitride, is treated to provide contact openings through to the silicon substrate by first depositing an undoped polycrystalline silicon layer over the silicon nitride layer, coating with photoresist, exposing and developing the photoresist to provide an opening to the polycrystalline silicon layer, etching through said latter layer with a particular etchant solution that etches large diameter openings at a faster rate than small diameter openings, and etching through the passivating layers whereby the desired contact opening is etched through to the substrate but pinhole openings less than about 2 microns in diameter in the photoresist layer are not propagated through the passivating layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.