Logic chip test system with path oriented decision making test pattern generator
US4204633A · kind A · utility
40Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 1978 |
| Grant date | May 27, 1980 |
| Priority date | — |
| Expiry date | Nov 20, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.