Parity for computer system having an array of external registers
US4234955A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1979 |
| Grant date | Nov 18, 1980 |
| Priority date | — |
| Expiry date | Jan 26, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For a computer system having an array of external registers which may be used as a data source or data destination, wherein such system uses an odd parity checking system, and wherein certain of the register position in the external array can be vacant, an improved parity checking configuration includes a plurality of parity bit latches, one for each location in the external register array. The parity bit latches are set by an initial microprogram load to provide an odd parity bit for each location in the external array of registers which is empty or which may be faulty, disabled or malfunctioning. This assures that when the external array is searched by row, that all of the array locations will provide the appropriate parity check regardless of whether a byte of information exists therein or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.