Thomas L. Jeremiah
21Patents
10h-index
32Co-inventors
75Inventor score
Filing activity: Mar 30, 1976 → Apr 15, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5287467A | Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit | Physics | 94 | Expired |
| US5303356A | System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag | Physics | 55 | Expired |
| US5504932A | System for executing scalar instructions in parallel based on control bits appended by compounding decoder | Physics | 47 | Expired |
| US5909694A | Multiway associative external microprocessor cache | Physics | 36 | Expired |
| US4021655A | Oversized data detection hardware for data processors which store data at variable length destinations | Physics | 29 | Expired |
| US5386531A | Computer system accelerator for multi-word cross-boundary storage access | Physics | 28 | Expired |
| US5446850A | Cross-cache-line compounding algorithm for scism processors | Physics | 25 | Expired |
| US5398321A | Microcode generation for a scalable compound instruction set machine | Physics | 21 | Expired |
| US8521982B2 | Load request scheduling in a cache hierarchy | Physics | 20 | Active |
| US5940877A | Cache address generation with and without carry-in | Physics | 14 | Expired |
| US5701430A | Cross-cache-line compounding algorithm for scism processors | Physics | 8 | Expired |
| US5039939A | Calculating AC chip performance using the LSSD scan path | Physics | 6 | Expired |
| US8347037B2 | Victim cache replacement | Emerging Cross-Sectional Technologies | 5 | Active |
| US6829702B1 | Branch target cache and method for efficiently obtaining target path instructions for tight program loops | Physics | 4 | Expired |
| US8117397B2 | Victim cache line selection | Emerging Cross-Sectional Technologies | 4 | Active |
| US8327073B2 | Empirically based dynamic control of acceptance of victim cache lateral castouts | Physics | 3 | Active |
| US4234955A | Parity for computer system having an array of external registers | Physics | 2 | Expired |
| US8327072B2 | Victim cache replacement | Physics | 1 | Active |
| US4964041A | Interruptible cache loading to assure immediate data access from cache | General | 1 | Revoked |
| US8166246B2 | Chaining multiple smaller store queue entries for more efficient store queue usage | Physics | 0 | Active |
| US7484052B2 | Distributed address arbitration scheme for symmetrical multiprocessor system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.