Semiconductor device

US4243997A · kind A · utility

Assignee

• Tokyo Shibaura Electric · JP

Inventors

• Kenji Natori · Kamakura, JP
• Fujio Masuoka · Yokohama, JP

Key dates

• Filing date: Oct 30, 1978
• Grant date: Jan 6, 1981
• Expiry date: Oct 30, 1998

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/025

Abstract

The first and second intrinsic semiconductor layers of thickness d are formed on a P type semiconductor substrate, keeping a prescribed interval therebetween, whereby a groove of depth d may be made between these layers. A dielectric layer is formed in such a way that it may cover a base and sides of the groove and a surface of the intrinsic semiconductor layer. On this surface, a gate electrode formed of polysilicon exists. Diffusion regions of a source and a drain of depths X.sub.sj and X.sub.dj are formed, in the neighborhood of groove sides, in the first and second intrinsic semiconductor layers (X.sub.sj, X.sub.dj d), resulting in an MOS transistor.