Fujio Masuoka
394Patents
32h-index
87Co-inventors
93Inventor score
Filing activity: Oct 5, 1976 → Apr 27, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4959812A | Electrically erasable programmable read-only memory with NAND cell structure | Physics | 528 | Expired |
| US4466081A | Semiconductor memory device | Physics | 287 | Expired |
| US5258635A | MOS-type semiconductor integrated circuit device | Emerging Cross-Sectional Technologies | 220 | Expired |
| US4939690A | Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation | Physics | 109 | Expired |
| US6727544B2 | Semiconductor memory including cell(s) with both charge storage layer(s) and control gate laterally surrounding island-like semiconductor layer | Electricity | 109 | Expired |
| US5371024A | Semiconductor device and process for manufacturing the same | Electricity | 87 | Expired |
| US5523980A | Semiconductor memory device | Physics | 79 | Expired |
| US4943944A | Semiconductor memory using dynamic ram cells | Physics | 74 | Expired |
| US4460835A | Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator | Electricity | 72 | Expired |
| US6870215B2 | Semiconductor memory and its production process | Physics | 65 | Expired |
| US4803529A | Electrically erasable and electrically programmable read only memory | Electricity | 60 | Expired |
| US6933556B2 | Semiconductor memory with gate at least partially located in recess defined in vertically oriented semiconductor layer | Electricity | 58 | Expired |
| US4706249A | Semiconductor memory device having error detection/correction function | Physics | 57 | Expired |
| US5615163A | Semiconductor memory device | Physics | 56 | Expired |
| US4926382A | Divided bit line type dynamic random access memory with charging/discharging current suppressor | Physics | 55 | Expired |
| US8039893B2 | CMOS inverter coupling circuit comprising vertical transistors | Electricity | 54 | Active |
| US4243997A | Semiconductor device | Electricity | 53 | Expired |
| US5075890A | Electrically erasable programmable read-only memory with NAND cell | Physics | 52 | Expired |
| US5453955A | Non-volatile semiconductor memory device | Physics | 52 | Expired |
| USRE35838E | Electrically erasable programmable read-only memory with NAND cell structure | General | 52 | Expired |
| US8080458B2 | Semiconductor device and manufacturing method thereof | Electricity | 52 | Active |
| US5831903A | Electrically erasable programmable read-only memory with threshold value controller for data programming and method of programming the same | Physics | 52 | Expired |
| US4687954A | CMOS hysteresis circuit with enable switch or natural transistor | Electricity | 48 | Expired |
| US5050125A | Electrically erasable programmable read-only memory with NAND cellstructure | Physics | 44 | Expired |
| US8188537B2 | Semiconductor device and production method therefor | Electricity | 42 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.