Memory device in which one type carrier stored during write controls the flow of the other type carrier during read
US4247916A · kind A · utility
Inventor
Key dates
| Filing date | Oct 30, 1979 |
| Grant date | Jan 27, 1981 |
| Priority date | — |
| Expiry date | Oct 30, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RAM device employs an array of dual gated transistor memory cells accessed by row and column decoding. A separate P type memory region is provided under the column gate which acquires holes as a function of the input data during the write cycle, for controlling the flow of an output electron current during the subsequent read cycle. The write holes flow from the substrate into the P memory region to record a "1" when both the row gate and the column gate are at a low positive potential. The write holes become trapped in the P memory region when the low write voltage on the row gate is replaced by a higher storage voltage. During the read cycle both gates are high, and electron current flows from source to drain along a continuous electron conductive path formed under both gates. The high row voltage causes electron conduction at the surface of the P substrate under the row gate by establishing an N type inversion layer. The high column voltage in combination with the positive charge of the write holes promotes the flow of read electrons under the column gate through a buried N channel adjacent to the P memory region. The read conductive path between the source and drain is formed…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.