IIL With partially spaced collars
US4259730A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1979 |
| Grant date | Mar 31, 1981 |
| Priority date | — |
| Expiry date | Apr 5, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/65
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I.sup.2 L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I.sup.2 L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I.sup.2 L structures each which are cross-coupled in the manner of a flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.