MOS Static decoding circuit
US4264828A · kind A · utility
15Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1978 |
| Grant date | Apr 28, 1981 |
| Priority date | — |
| Expiry date | Nov 27, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A metal-oxide-semiconductor (MOS) static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit may be laid-out along array lines where the lines have a pitch of approximately 12.25 microns. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.