I-C Wafer incorporating junction-type field-effect transistor
US4266233A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1979 |
| Grant date | May 5, 1981 |
| Priority date | — |
| Expiry date | Dec 14, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon wafer incorporating several semiconductor components, among them a junction-type field-effect transistor (J-FET) of low pinch-off voltage connectable as a resistor, comprises a substrate of P-type conductivity with an insular layer of N.sup.+ conductivity penetrated by one or more enclaves of substrate material. Thereafter, a stratum of N-doped silicon is epitaxially grown on the substrate, with formation of rising zones above each enclave and around the buried N.sup.+ layer which are heavily doped with P-type impurities to act as source connections or sinkers for an FET channel formed by the enclave or enclaves and as a barrier junction surrounding a section of the N-doped stratum which becomes the gate of the FET while the substrate serves as the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.