Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4267012A · kind A · utility
45Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1979 |
| Grant date | May 12, 1981 |
| Priority date | — |
| Expiry date | Apr 30, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for patterning regions on a semiconductor structure comprises the steps of forming a first layer of an alloy of tungsten and titanium on the semiconductor structure, forming a conductive layer of aluminum or chemically similar material on the surface of the tungsten-titanium alloy, removing the undesired portions of the conductive layer by etching with a plasma and removing the thereby exposed portions of the tungsten-titanium alloy layer by chemical etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.