NMOS Voltage reference generator
US4267501A · kind A · utility
14Cited by
4References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 21, 1979 |
| Grant date | May 12, 1981 |
| Priority date | — |
| Expiry date | Jun 21, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/247
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An NMOS voltage regulator circuit generates a reference voltage for comparison with, for example, TTL logic levels. A resistive voltage divider coupled to a 5 volt source produces a voltage of, for example, 1.5 volts which is applied to the non-inverting input of a differential amplifier. The reference voltage appears at the inverting input of the differential amplifier. Field effect transistor means are provided to raise or lower the voltage at the inverting input depending on whether a negative or positive excursion has taken place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.