Stephen Lee Smith
36Patents
10h-index
25Co-inventors
75Inventor score
Filing activity: Jun 21, 1979 → Nov 22, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4727309A | Current difference current source | Physics | 62 | Expired |
| US4791326A | Current controlled solid state switch | Electricity | 54 | Expired |
| US4689504A | High voltage decoder | Electricity | 48 | Expired |
| US4437171A | ECL Compatible CMOS memory | Electricity | 39 | Expired |
| US5553012A | Exponentiation circuit utilizing shift means and method of using same | Physics | 31 | Expired |
| US5600581A | Logarithm/inverse-logarithm converter utilizing linear interpolation and method of using same | Physics | 21 | Expired |
| US4289982A | Apparatus for programming a dynamic EPROM | Electricity | 15 | Expired |
| US4267501A | NMOS Voltage reference generator | Physics | 14 | Expired |
| US9727675B2 | Parameter extraction of DFT | Physics | 12 | Active |
| US4968903A | Combinational static CMOS logic circuit | Electricity | 10 | Expired |
| US4237547A | Program decoder for shared contact eprom | Physics | 9 | Expired |
| US4464736A | In-package E.sup.2 PROM redundancy | Physics | 7 | Expired |
| US9530027B2 | Device lock for transit | Electricity | 7 | Active |
| US6259720A | Versatile digital signal processing system | Electricity | 4 | Expired |
| US5726924A | Exponentiation circuit utilizing shift means and method of using same | Physics | 3 | Expired |
| US9852242B2 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Physics | 3 | Active |
| US5608663A | Computational array circuit for providing parallel multiplication | Physics | 3 | Expired |
| US9836563B2 | Iterative simulation with DFT and non-DFT | Physics | 3 | Active |
| US9881111B2 | Simulation scaling with DFT and non-DFT | Physics | 3 | Active |
| US5752012A | Computational array with self timed computational element and method of self timed calculation | Physics | 3 | Expired |
| US10489212B2 | Adaptive parallelization for multi-scale simulation | Physics | 2 | Active |
| US10606968B2 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Physics | 1 | Active |
| US10776560B2 | Mapping intermediate material properties to target properties to screen materials | Physics | 1 | Active |
| US10831957B2 | Simulation scaling with DFT and non-DFT | Physics | 1 | Active |
| US10102318B2 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.