Multiprocessor mechanism for handling channel interrupts
US4271468A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1979 |
| Grant date | Jun 2, 1981 |
| Priority date | — |
| Expiry date | Nov 6, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program. An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty. A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs. In each CP, acceptance determining circuits c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.