William C. Van Loo
32Patents
20h-index
19Co-inventors
82Inventor score
Filing activity: Nov 6, 1979 → Jun 5, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5655100A | Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system | Physics | 275 | Expired |
| US5634068A | Packet switched cache coherent multiprocessor system | Physics | 119 | Expired |
| US5905998A | Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system | Physics | 110 | Expired |
| US4271468A | Multiprocessor mechanism for handling channel interrupts | Physics | 104 | Expired |
| US5644753A | Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system | Physics | 103 | Expired |
| US5581729A | Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system | Physics | 92 | Expired |
| US5684977A | Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system | Physics | 88 | Expired |
| US5692197A | Method and apparatus for reducing power consumption in a computer network without sacrificing performance | Physics | 82 | Expired |
| US6233615A | System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes | Electricity | 82 | Expired |
| US5247648A | Maintaining data coherency between a central cache, an I/O cache and a memory | Physics | 75 | Expired |
| US5657472A | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor | Physics | 74 | Expired |
| US5263142A | Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices | Physics | 65 | Expired |
| US5892957A | Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system | Physics | 47 | Expired |
| US5689713A | Method and apparatus for interrupt communication in a packet-switched computer system | Physics | 40 | Expired |
| US6101565A | System for multisized bus coupling in a packet-switched computer system | Physics | 30 | Expired |
| US5854906A | Method and apparatus for fast-forwarding slave request in a packet-switched computer system | Physics | 25 | Expired |
| US5710891A | Pipelined distributed bus arbitration system | Physics | 25 | Expired |
| US5919265A | Source synchronization data transfers without resynchronization penalty | Electricity | 23 | Expired |
| US6065052A | System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes | Electricity | 21 | Expired |
| US5161162A | Method and apparatus for system bus testability through loopback | Physics | 20 | Expired |
| US6463472B1 | System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes | Electricity | 19 | Expired |
| US5864677A | System for preserving sequential ordering and supporting nonidempotent commands in a ring network with busy nodes | Electricity | 17 | Expired |
| US5852718A | Method and apparatus for hybrid packet-switched and circuit-switched flow control in a computer system | Physics | 17 | Expired |
| US5907485A | Method and apparatus for flow control in packet-switched computer system | Physics | 17 | Expired |
| US6381664B1 | System for multisized bus coupling in a packet-switched computer system | Physics | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.