Process for making CMOS field-effect transistors
US4277291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1980 |
| Grant date | Jul 7, 1981 |
| Priority date | — |
| Expiry date | Jan 21, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/07
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Two patches of silicon nitride are formed above spaced-apart regions of an n-type substrate (2) on an overlying oxide layer (8) of small thickness. Arsenic ions are then implanted through the oxide layer in substrate areas not covered by the patches whereupon one patch (10a) and an adjoining portion of the oxide layer are covered by a photoresist mask (14), leaving unprotected the second patch (10b) and an oxide portion adjacent thereto. The wafer is then bombarded with boron ions, first at a relatively low energy level to penetrate the last-mentioned oxide portion and then at a higher energy level with additional penetration of the second patch (10b) to form a p-well (18) bounded by a p+ guard zone (20); the previously implanted arsenic ions in the unbombarded area form an n+ guard zone (22). Next, the wafer is subjected to a heat treatment in an oxidizing atmosphere with resulting deepening of the guard zones and the p-well and with growth of the oxide layer especially in areas not overlain by the patches whose subsequent removal, together with other oxide portions except for a residue forming two insulating gate supports (24a, 24b), exposes source and drain areas of the p-well (…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.