Latch circuit operable as a D-type edge trigger
US4277699A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1979 |
| Grant date | Jul 7, 1981 |
| Priority date | — |
| Expiry date | Jul 26, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a `D` type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.