Thomas W. Williams
29Patents
18h-index
23Co-inventors
81Inventor score
Filing activity: Jun 30, 1976 → May 12, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4503386A | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks | Electricity | 65 | Expired |
| US6385750B1 | Method and system for controlling test data volume in deterministic test pattern generation | Physics | 54 | Expired |
| US6615380B1 | Dynamic scan chains and test pattern generation methodologies therefor | Physics | 53 | Expired |
| US6950974B1 | Efficient compression and application of deterministic patterns in a logic BIST architecture | Physics | 51 | Expired |
| US4293919A | Level sensitive scan design (LSSD) system | Physics | 48 | Expired |
| US6993694B1 | Deterministic bist architecture including MISR filter | Physics | 41 | Expired |
| US4509008A | Method of concurrently testing each of a plurality of interconnected integrated circuit chips | Physics | 39 | Expired |
| US4063080A | Method of propagation delay testing a level sensitive array logic system | Electricity | 39 | Expired |
| US6807646B1 | System and method for time slicing deterministic patterns for reseeding in logic built-in self-test | Physics | 34 | Expired |
| US4051352A | Level sensitive embedded array logic system | Electricity | 33 | Expired |
| US4074851A | Method of level sensitive testing a functional logic system with embedded array | Electricity | 28 | Expired |
| US6434733B1 | System and method for high-level test planning for layout | Physics | 26 | Expired |
| US6405355B1 | Method for placement-based scan-in and scan-out ports selection | Physics | 25 | Expired |
| US6990619B1 | System and method for automatically retargeting test vectors between different tester types | Physics | 24 | Expired |
| US6631344B1 | Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation | Physics | 20 | Expired |
| US4277699A | Latch circuit operable as a D-type edge trigger | Electricity | 20 | Expired |
| US6766501B1 | System and method for high-level test planning for layout | Physics | 19 | Expired |
| US4071902A | Reduced overhead for clock testing in a level system scan design (LSSD) system | Physics | 19 | Expired |
| US7418640B2 | Dynamically reconfigurable shared scan-in test architecture | Physics | 18 | Expired |
| US6453437B1 | Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation | Physics | 16 | Expired |
| US7900105B2 | Dynamically reconfigurable shared scan-in test architecture | Physics | 15 | Active |
| US7814444B2 | Scan compression circuit and method of design therefor | Physics | 12 | Active |
| US4726023A | Determination of testability of combined logic end memory by ignoring memory | Physics | 7 | Expired |
| US7774663B2 | Dynamically reconfigurable shared scan-in test architecture | Physics | 7 | Active |
| US7669098B2 | Method and apparatus for limiting power dissipation in test | Physics | 7 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.