One word buffer memory system
US4292674A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 1979 |
| Grant date | Sep 29, 1981 |
| Priority date | — |
| Expiry date | Jul 27, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system which already includes an address register, a randomly accessible memory unit, a data-in register and a data-out register is converted to also include a one word buffer memory with the addition of only a few components. A plus one adder is included for incrementing the address contained in the address register and the result is then stored in an address plus one register. The randomly accessible memory unit may be accessed with the address plus one register when it has completed the normal access with the address register pending a new request. The resultant memory data from this access at the incremented address is stored in a one word internal register which is a buffer to the randomly accessible memory unit. Since such access is noninterfering with and overlapped in time with the overall memory system communication with a requestor, and pending any new request to the randomly accessible memory stores, it serves to efficiently create a buffer store only for the next consecutive address. When a new request from a requestor external to the memory system occurs, a comparator compares the new address as becomes lodged in the address register and the immediately previo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.