Storage cell simulation for generating a reference voltage for semiconductor stores in mtl technology
US4313177A · kind A · utility
3Cited by
12References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1980 |
| Grant date | Jan 26, 1982 |
| Priority date | — |
| Expiry date | May 12, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/65
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each other in an N-type trough of semiconductor material. The elongated P-type regions are alternately designed as collector and Injector strips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.