Method of producing integrated MOS circuits via silicon gate technology

US4313256A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventor

• Dietrich Widmann · Unterhaching, DE

Key dates

• Filing date: Jan 7, 1980
• Grant date: Feb 2, 1982
• Expiry date: Jan 7, 2000

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76888
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of producing integrated MOS circuits via silicon gate technology with self-adjusting contacts by using silicon nitride masking. In accordance with this method, after etching contact holes for the formation of contacts between monocrystalline doped regions (5) and polysilicon regions (4, 8), or metal interconnections (12), an insulating layer 10 is produced. This insulating layer is produced, after appropriate masking with an oxidation-inhibiting silicon nitride layer of the regions to be connected, from a layer (8) which is additionally applied and doped to correspond to the doped regions in the silicon substrate, and which is converted by local oxidation into the insulating layer (10). This process provides extremely high packing density of circuit elements.