Dense high performance JFET compatible with NPN transistor formation and merged BIFET
US4314267A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1980 |
| Grant date | Feb 2, 1982 |
| Priority date | — |
| Expiry date | Feb 4, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/409
Abstract
A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.