Method and device for testing a sequential circuit divided into a plurality of partitions
US4317200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1979 |
| Grant date | Feb 23, 1982 |
| Priority date | — |
| Expiry date | Oct 19, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
For test, a sequential circuit operable in a normal and a shift mode is logically divided into a plurality of partitions, each comprising a first and a second sequence of registers. A testing device specifies the first sequence in each partition, one partition after another, and supplies the registers of the specified first sequence, in the shift mode, with a test pattern prescribed for the specified partition. A pattern resulting from the test pattern is supplied in the normal mode to the registers of the second sequence in the specified partition and shifted out thereof subsequently in the shift mode to be compared with a correct or reference pattern predetermined for the test pattern for detection of a fault. For location of the fault in the specified partition, the test and the shifted-out patterns are combined into a combined pattern, which is supplied to the registers of the first and the second sequences in the normal mode following the shift mode in which the fault is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.