Self-aligned metal process for integrated injection logic integrated circuits
US4322883A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1980 |
| Grant date | Apr 6, 1982 |
| Priority date | — |
| Expiry date | Jul 8, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I.sup.2 L) technology. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. The first insulating layer is removed in areas designated to contain integrated injection logic devices. A layer of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.