Reducing charging effects in charged-particle-beam lithography
US4323638A · kind A · utility
11Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1980 |
| Grant date | Apr 6, 1982 |
| Priority date | — |
| Expiry date | Aug 18, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S430/143
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charge-conducting medium during lithography. The pattern delineated in the resist layer (56) is transferred into the film (16) and subsequently into an underlying layer (20). The film (16) is highly compatible with standard lithographic and etching processes used to fabricate LSI and VLSI circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.