Method of manufacturing semiconductor memory device having memory cell elements composed of a transistor and a capacitor

US4335505A · kind A · utility

Assignee

• VLSI Technology Research Association · JP

Inventors

• Hiroshi Shibata · Amuru, UG
• Tatsuya Enomoto · Itami, JP

Key dates

• Filing date: Dec 26, 1979
• Grant date: Jun 22, 1982
• Expiry date: Dec 26, 1999

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A method for forming semiconductor memory devices each including either an MNOS-type or MOS-type transistor and an MNOS-type capacitor. Upon a silicon substrate there is formed a thick layer of oxide which defines the individual cells and provides separation therebetween. Exposed portions of the substrate are thermally oxidized to form a layer of thermal oxide upon which is subsequently deposited a layer of silicon nitride and a layer of polycrystalline silicon. The polycrystalline silicon is then masked and portions there are removed through apertures and the mask. The substrate is then irradiated at a non-perpendicular angle through the apertures in the mask and predetermined remaining portions of the layer of thermal oxide are removed. Exposed portions of the substrate at this point are diffused with an impurity of the opposite conductivity type to the substrate. A second polycrystalline silicon layer is then formed to provide bit lines for each memory cell and simultaneously an opposing electrode of the corresponding capacitors. A second thick oxide layer is then formed with a metal interconnection layer deposited thereon for forming the connection lines to each memory cell.