Process for fabricating a bipolar transistor
US4338138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1980 |
| Grant date | Jul 6, 1982 |
| Priority date | — |
| Expiry date | Mar 3, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.