High performance PNP and NPN transistor structure

US4339767A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Cheng T. Horng · San Jose, US
• Richard R. Konian · Poughkeepsie, US
• Robert O. Schwenker · Hopewell Junction, US
• Armin Wieder · Gauting, DE

Key dates

• Filing date: May 5, 1980
• Grant date: Jul 13, 1982
• Expiry date: May 5, 2000

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/63
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.