Vertical channel field effect transistor
US4343015A · kind A · utility
44Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 1980 |
| Grant date | Aug 3, 1982 |
| Priority date | — |
| Expiry date | May 14, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
Abstract
Improved high frequency GaAs FETs have a higher breakdown voltage, lower input gate capacitance and lower source (or drain) resistance. A preferentially etched groove structure yields parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Every finger intersects a high resistivity, semi-insulating region which surrounds the active device area and is fabricated by high energy particle bombardment. Metal gates are deposited within the grooves on three sides of the trapezoidal fingers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.