Bus error recognition for microprogrammed data processor
US4348722A · kind A · utility
18Cited by
9References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1980 |
| Grant date | Sep 7, 1982 |
| Priority date | — |
| Expiry date | Apr 3, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage means is reset. If, however, a halt signal accompanies the bus error signal, the storage means is not reset and the bus cycle is rerun when the halt signal terminates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.