Narrow channel length MOS field effect transistor with field protection region for reduced source-to-substrate capacitance
US4350991A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1979 |
| Grant date | Sep 21, 1982 |
| Priority date | — |
| Expiry date | Jun 22, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/357
Abstract
A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.