Process for suppressing electromigration in conducting lines formed on integrated circuits by control of crystalline boundary orientation
US4352239A · kind A · utility
15Cited by
1References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 17, 1980 |
| Grant date | Oct 5, 1982 |
| Priority date | — |
| Expiry date | Apr 17, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/927
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for suppressing electromigration in conducting lines formed on integrated circuit structures includes the steps of forming the conducting lines on the integrated circuit structure and heat treating the lines to cause the average grain size in the lines to become larger than the width of the conducting lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.