Method of producing low-resistance diffused regions in IC MOS semiconductor circuits in silicon-gate technology metal silicide layer formation
US4356622A · kind A · utility
64Cited by
9References
9Claims
0Family size
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Key dates
| Filing date | Jun 9, 1980 |
| Grant date | Nov 2, 1982 |
| Priority date | — |
| Expiry date | Jun 9, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/934
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Low-resistance diffused regions useful as current-supply paths in IC MOS semiconductor circuits in silicon-gate technology are produced by forming a metal silicide on a doped polysilicon layer positioned on a substrate, applying a SiO.sub.2 layer over the silicide layer, structuring the resultant SiO.sub.2 -silicide-polysilicon triple layer in such a manner that areas of the substrate where the low resistance diffused regions are desired remain covered, thereafter executing gate oxidation and completing fabrication of the desired circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.