Method for forming IGFET devices having improved drain voltage characteristics
US4369072A · kind A · utility
32Cited by
18References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1981 |
| Grant date | Jan 18, 1983 |
| Priority date | — |
| Expiry date | Jan 22, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of providing less than one micron p-n junction regions for IGFET devices in which a high concentration of arsenic is implanted so that its peak lies near the surface of a semiconductor substrate. Phosphorus is also implanted with an energy to provide a maximum concentration below that of the arsenic and of a magnitude at least one order of magnitude less than that of arsenic. An oxidation/anneal step thermally diffuses the implanted ions to form a junction less than one micron in thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.