Method of manufacturing semiconductor device utilizing a lift-off technique

US4371423A · kind A · utility

Assignee

• VLSI Technology Research Association · JP

Inventors

• Rokuro Yoshizawa · Neuss, DE
• Satoshi Shinozaki · Yokohama, JP

Key dates

• Filing date: Sep 3, 1980
• Grant date: Feb 1, 1983
• Expiry date: Sep 3, 2000

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/033
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of manufacturing a semiconductor device comprising a step of covering a principal surface of a semiconductor substrate having semiconductor regions formed therein and at least partly provided with a silicon oxide film with a cover film having an etching characteristic different from that of the oxide film, a step of forming a first deposition layer having a higher etching speed than that of the cover layer on the cover layer, a step of forming a second deposition layer having a lower etching speed than that of the first deposition layer on the first deposition layer, a step of etching away portions of the second and first deposition layers and cover layer corresponding to a wiring pattern in succession, a step of etching the exposed portions of the silicon oxide film with the cover layer having the openings as a mask to thereby form contact holes with respect to the semiconductor substrate, and a step of forming wiring leads by depositing a wiring metal and etching away the first deposition layer and thus lifting off the second deposition layer and wiring metal portions thereon.