Polysilicon-base self-aligned bipolar transistor process
US4381953A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1981 |
| Grant date | May 3, 1983 |
| Priority date | — |
| Expiry date | Aug 17, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/051
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a process for forming an improved bipolar transistor in a silicon substrate of a first conductivity type, said silicon substrate having a planar surface, a subcollector region of a second conductivity type formed in said substrate, an epitaxial layer of said second conductivity type formed on said planar surface of said substrate, and first, second and third spaced apart recessed oxide isolation regions extending from the planar surface of said epitaxial layer into said substrate, a subcollector reach-through region positioned between said second and third recessed oxide isolation regions, said subcollector reach-through region extending from said planar surface of said epitaxial layer to said subcollector region, said process including the following steps: deposit, using chemical vapor deposition techniques, a layer of doped polysilicon on the exposed surface of said substrate said dopant being of said first conductivity type; deposit, using chemical vapor deposition techniques a first layer of silicon dioxide on said polysilicon layer; deposit a layer of photoresist on said first layer of silicon dioxide; utilizing photolithography, mask off an intended intrinsic bas…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.