Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes
US4389257A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1981 |
| Grant date | Jun 21, 1983 |
| Priority date | — |
| Expiry date | Jul 30, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.