Larry A. Nesbit
10Patents
8h-index
23Co-inventors
72Inventor score
Filing activity: Jul 30, 1981 → May 26, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4601779A | Method of producing a thin silicon-on-insulator layer | Electricity | 92 | Expired |
| US5573633A | Method of chemically mechanically polishing an electronic component | Electricity | 45 | Expired |
| US4558508A | Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step | Emerging Cross-Sectional Technologies | 40 | Expired |
| US4532700A | Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer | Emerging Cross-Sectional Technologies | 38 | Expired |
| US4389257A | Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes | Emerging Cross-Sectional Technologies | 18 | Expired |
| US7187085B2 | Semiconductor device including dual damascene interconnections | Electricity | 13 | Expired |
| US6759332B2 | Method for producing dual damascene interconnections and structure produced thereby | Electricity | 10 | Expired |
| US5795826A | Method of chemically mechanically polishing an electronic component | Electricity | 9 | Expired |
| US7125790B2 | Inclusion of low-k dielectric material between bit lines | Electricity | 6 | Expired |
| US6890815B2 | Reduced cap layer erosion for borderless contacts | Electricity | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.