Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors
US4389768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1981 |
| Grant date | Jun 28, 1983 |
| Priority date | — |
| Expiry date | Apr 17, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/87
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for the fabrication of a gallium arsenide (GaAs) metal-semiconductor field effect transistor (MESFET) is described. The method requires the step of providing a semi-insulating GaAs substrate having thereon a layer of n doped GaAs and another layer of n+ doped Ga.sub.1-x Al.sub.x As, the latter being used as a diffusion source for n dopants in selectively doping the n GaAs layer underneath. The fabrication method further includes the step of employing highly directional reactive ion etching on silicon nitride to build insulating side walls thereby to effect the self-alignment of the gate of the MESFET with respect to its source and drain. GaAs MESFET fabricated using this method has its source and drain in close proximity having its gate therebetween. Utilizing the disclosed method, conventional photolithographic techniques can be employed to produce submicron self-aligned GaAs MESFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.