Saturation-limited bipolar transistor device
US4390890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1980 |
| Grant date | Jun 28, 1983 |
| Priority date | — |
| Expiry date | Jun 26, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/63
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region. A first N type region is formed through the P type region extending from the surface of the epitaxial layer to the subcollector dividing the P type region into first and second sections which serve as the PNP collector region and the NPN base region, respectively. A second N type region is forme…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.