Selective encapsulation, controlled atmosphere annealing for III-V semiconductor device fabrication
US4396437A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1981 |
| Grant date | Aug 2, 1983 |
| Priority date | — |
| Expiry date | May 4, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3245
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A post-ion implantation annealing technique is provided to remove implantation damage in the active region of III-V (e.g., GaAs) semiconductor devices formed in a III-V semi-insulating substrate and separated by a field region. The technique involves applying a dielectric encapsulation selectively over the device active area and annealing in a controlled reducing atmosphere which includes the Group V element (e.g., arsenic). The dielectric encapsulant over the active region permits migration of the species employed to render the substrate semi-insulating (e.g., Cr in GaAs substrates), thereby resulting in high carrier mobility in the active region. Without encapsulation, migration of the species in the field region is substantially suppressed, thereby resulting in good inter-device isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.