Monolithic static memory cell and method for its operation
US4396996A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 1981 |
| Grant date | Aug 2, 1983 |
| Priority date | — |
| Expiry date | Aug 19, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A monolithic static memory cell has two cross-coupled inverters each comprised of a series connection of a field effect switching transistor and a load element designed as a field effect transistor. The field effect transistors forming the load elements have their channel resistances of different values. A gate insulating layer of one of the load element field effect transistors has its charge state altered, preferably by electron beam writing, so that a change in a threshold voltage of the one transistor results in a change of its channel resistance relative to the channel resistance of the other load element transistor if it was under before the selective altering, or vice-versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.