On-chip Delta-I noise clamping circuit
US4398106A · kind A · utility
16Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1980 |
| Grant date | Aug 9, 1983 |
| Priority date | — |
| Expiry date | Dec 19, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/467
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. An impedance path is defined between each of the chips and the power supply to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.