Etching apparatus and method
US4400235A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1982 |
| Grant date | Aug 23, 1983 |
| Priority date | — |
| Expiry date | Mar 25, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68771
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a plasma-assisted dry etching process designed to pattern VLSI devices, a relatively high and uniform etch rate exhibiting low contamination is achieved over the entire surface extent of each wafer to be etched. This is accomplished by mounting the wafers in a unique fashion on one of two spaced-apart electrodes in the reaction chamber of a dry etching system. In particular, the front surface of each wafer is maintained in substantially the same plane as that of surrounding dielectric material. Additionally, the thickness of the surrounding dielectric material is designed to be considerably greater than the thickness of any dielectric material in contact with the back surface of each wafer. In that way, the entire front surface extent of each wafer is influenced by a relatively uniform electric field. Moreover, the available field in the chamber is in effect focussed onto the wafer surfaces, thereby achieving a relatively high etch rate characterized by low contamination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.