Wait circuitry for interfacing between field maintenance processor and device specific adaptor circuit
US4414664A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1981 |
| Grant date | Nov 8, 1983 |
| Priority date | — |
| Expiry date | Feb 23, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A field maintenance processor including a microprocessor that effects transparent refreshing of a dynamic memory includes a counter circuit which times the duration of the "wait" signal produced by a slow memory or a slow peripheral device accessed by the processor. The counter circuit produces a "wait enable" signal which enables the "wait" signal to produce an "enabled wait" signal that is conducted to a wait input of the processor for only a predetermined time, to ensure transparent refreshing of the entire dynamic memory. If the "wait" signal produced by the slow memory device has not ceased when the predetermined time has elapsed, the "wait enable" signal disappears, causing the "enabled wait" signal also to disappear. The disappearance of the "wait enable" signal also causes a "wait interrupt" signal to be generated and transmitted to the microprocessor, resulting in execution of an interrupt routine to determine which instruction execution was earlier halted in response to the "enabled wait" signal. The entire dynamic memory is transparently refreshed during execution of the interrupt routine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.